ID:16469 Source REFCLK I/O cannot be routed using dedicated clock routing for <name>, placed at <location>

CAUSE: The specified global clock driver is fed by an input pin (or pair of differential input pins) that has been placed onto a dedicated REFCLK input pin location, but the fitter was unable to route the signal to the global clock driver with dedicated clock routing. This signal will be routed to the global clock driver input using the FPGA core routing fabric. To improve jitter performance and reduce clock skew, Intel recommends using dedicated REFCLK I/Os to drive global clocks through dedicated clock routing. This can be caused if the clock driver was placed to a location that can not be driven from the specified refclk I/O location, or if there is routing congestion between the refclk I/O location and the global clock driver.

ACTION: To improve jitter performance and reduce clock skew between the I/O input and the global clock driver, modify your design or the placement constraints so the clock input signal can be fed to the the specified global clock driver from a REFCLK input pin location, through dedicated routing.