ID:204000 Port <name1> is changed into <name2> because it has negative index

CAUSE: You directed the Quartus Prime software to generate an output netlist file for the top-level design entity. However, in the design there are arrays using negative indexing. VHDL language does not support negative indexing, therefore members which have negative indices are changed into single-bit ports.

ACTION: If you are using a test bench with the output netlist file, fix its port interface to match the newly generated netlist output file. To avoid receiving this message in the future, avoid using negative array indexing.