ID:21446 Verilog HDL info at <location>: set runtime flag 'veri_create_unique_hierarchy_for_module_instantiated_in_VHDL' to support such mixed language design

CAUSE: Intel Quartus Prime Synthesis generated the specified info message for the specified location in a Design File.

ACTION: No action is required. A future version of the Intel Quartus Prime software will provide more extensive Help for this info message.