ID:13534 Verilog HDL Assignment information at <location>: truncated unsized constant literal with size <number> to size <number> with no loss of information

CAUSE: In an assignment at the specified location in a Verilog Design File (.v), you assigned an unsized constant value to a target whose size is too small to store the entire constant value. As a result, Quartus Prime Integrated Synthesis truncated the value to match the size of the target. This message usually results from assignments like assign o = 0; because unsized constants in Verilog are 32 bits. In this case, however, the truncation did not result in any information loss.

ACTION: If this behavior is correct, then no action is required. Otherwise, to avoid receiving this message in the future, increase the size of the target or decrease the size of the assigned value until both target and assigned value have the same size.