ID:16365 The following timing edges are non-unate. Timing analysis results may be pessimistic.

CAUSE: A non-unate timing edge was found in the clock network. The Timing Analyzer will assume that registers clocked beyond this node may launch/latch on either the rising or falling edge of the clock. This behavior can be the result of gated logic such as an XOR, select path of a MUX, etc.

ACTION: No action may be necessary. If applicable, the non-unate logic elements in this clock path can be changed to those known to exhibit a pos-unate or neg-unate behavior. Alternatively, a generated clock can be created on the output of the logic element to explicitly specify the desired waveform. Alternatively, the set_sense command may be used to indicate which sense to analyze relative to the clock source.