ID:276009 RAM logic "<name>" is uninferred due to unsupported read-during-write behavior

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the read-during-write behavior of the RAM is not supported by the RAM hardware in the device family.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, change the read-during-write behavior of the RAM logic to be compatible with the RAM hardware of the device family.