ID:276008 RAM logic "<name>" is uninferred due to illegal secondary signals in read logic

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the read logic for the RAM has secondary signals that are not compatible with the RAM in the device family.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, remove the incompatible signals from the RAM logic.