ID:276004 RAM logic "<name>" is uninferred due to inappropriate RAM size

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the RAM size is too small to be efficiently implemented in hardware.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, turn on the Allow Any RAM Size For Recognition logic option.