ID:276005 RAM logic "<name>" is uninferred due to device family not having RAM hardware

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the device family does not have dedicated RAM hardware.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, choose a device family that has dedicated RAM hardware.