ID:176406 Following PLLs have a fixed counter order and cannot be changed; they may have forced some signals to use the same Clock Control Block

CAUSE: Some of the phase-locked loops (PLLs) have a fixed counter order, and the compiler is not able to change the counter order to fit the global signals specified in the design. This may CAUSE errors because some signals cannot use the same Clock Control Block. Situations that lead to a PLL using a fixed counter order include applying the Preserve PLL Counter Order assignment to a PLL, using PLL dynamic reconfiguration, or specifying the PLL using advanced parameters.

ACTION: Move the PLL to a different location, or do not fix the counter order of the PLL, if possible.