ID:176533 DLL "<name>" (in low jitter mode) requires up to <number> clock cycles to generate correct delay control settings on system power-up

CAUSE: On system power-up, the specified delay locked loop (DLL) requires up to the specified number of clock cycles to generate the correct delay control settings. DQS I/O pins fed by the delayctrlout port of the DLL will only generate the correct phase-shift after the specified number of cycles (on system power-up).

ACTION: No action is required.