ID:181055 PLL output counters 0-3 or 14-17 is not used for driving the PHY clock tree in your Stratix V device.

CAUSE: PHY clock tree is driven by one or more hi-skew PLL outputs.

ACTION: Use the set_location_assignment <PLL counter location> -to <PLL output signal> to constrain the phase-locked loop (PLL) counters that drive the PHY clock tree.