ID:13838 VHDL Wait Statement error at <location>: condition clause uses 'EVENT predefined attribute to wait on an arbitrary signal event -- Wait Statement must test for signal edge

CAUSE: In a Wait Statement at the specified location in a VHDL Design File (.vhd), you directed a process to wait on an arbitrary signal event by using the 'EVENT predefined attribute in a condition clause that has the UNTIL keyword. For example, you may have used clk'EVENT in the condition clause. However, if a condition clause contains an 'EVENT condition, you must combine the condition with another, level-test condition that tests for a fully-qualified signal edge. For example, in a condition clause that contains clk'EVENT, you can use clk = '1' to test for the rising edge of the signal clk.

ACTION: Make sure the condition clause with the UNTIL keyword in the Wait Statement does not contain the 'EVENT predefined attribute without an additional level-test condition for the same signal.