ID:13817 VHDL aggregate error at <location>: aggregate contains one value for two or more elements, but elements must have same type

CAUSE: In a VHDL Design File (.vhd) at the specified location, you used an aggregate for a record type object. In the aggregate, you specified one value for two or more of the object elements. However, the elements do not all have the same type. For example, the first Signal Assignment Statement in the following code uses the OTHERS choice to specify the value 1 for the elements ex2 and ex3. The second Signal Assignment Statement specifies the value 3 for the elements ex1 and ex2. However, ex1 and ex3 have an integer type, and ex2 has a string type.

TYPE example IS
   RECORD
      ex1 : INTEGER range 1 to 5;
      ex2 : STRING
      ex3 : INTEGER range 1 to 7;
   END example;
SIGNAL exa : example;
  
               
exa <= (ex1 => 3, OTHERS => 1);
exa <= (ex1 | ex2 => 3, ex3 => 2);

When you specify a value for two or more object elements, the elements must all have the same type.

ACTION: Make sure all the elements for a value in the aggregate have the same type by changing the values in the aggregate or changing the element types in the Type Declaration. In the previous example, you can use the following aggregates, or change ex2 to have an integer type in the Type Declaration:

exa <= (ex1 => 3, ex2 => "1", OTHERS => 1);
exa <= (ex1 => 3,  ex2 => "3", ex3 => 2);