ID:13956 VHDL Binding Indication error at <location>: binding indication with OPEN entity aspect cannot contain generic or port bindings

CAUSE: In a binding indication at the specified location in a VHDL Design File (.vhd), you used an OPEN entity aspect to indicate that the target component should be left unbound; however, you also specified generic and/or port bindings. The VHDL language does not allow you to specify generic or port bindings if the entity aspect is OPEN.

ACTION: Remove the generic and/or port bindings or bind the component to a specific entity or configuration.