ID:13813 VHDL error at <location>: can't access enumeration literal to the right of enumeration literal "<name>" in enumeration type <name>

CAUSE: In a VHDL Design File (.vhd) at the specified location, you attempted to access an enumeration literal to the right of the specified enumeration literal in the specified enumeration type. However, the specified enumeration literal is the last enumeration literal in the enumeration type, and therefore it has no enumeration literals to its right for Quartus Prime Integrated Synthesis to access. For example, the 'SUCC predefined attribute in the following code attempts to access an enumeration literal that is positioned to the right of enumeration literal st2 in the enumeration type StateType. However, st2 is the last enumeration literal in StateType.

TYPE StateType IS (st0, st1, st2);
SIGNAL current_state: StateType;
SIGNAL next_state: StateType;
 
               
PROCESS(i, current_state)
BEGIN
   current_state <= st2;
   CASE current_state is
      WHEN st2 =>
         next_state <= StateType'SUCC(st2);
      WHEN others =>
         next_state <= st2;
   END CASE;
END PROCESS;