ID:13696 VHDL Loop Statement error at <location>: infinite loops are not supported for synthesis

CAUSE: In a Loop Statement at the specified location in a VHDL Design File (.vhd), you specified a loop that does not terminate. Quartus Prime Integrated Synthesis does not support infinite loops for synthesis. This message may occur due to an error in the Loop Statement's WHILE iteration scheme, FOR iteration scheme, or Exit Statement; or because you did not increment the variable for the loop.

ACTION: Make sure that the Loop Statement specifies a loop that terminates.