ID:13390 Verilog HDL unsupported feature error at <location>: Release Statement not supported for processing with Quartus Prime Integrated Synthesis

CAUSE: In a Verilog Design File (.v) at the specified location, you used a Release Statement. Although Release Statements are supported in Verilog HDL, they are not supported for processing with Quartus Prime Integrated Synthesis. A Release Statement is used in conjunction with a Force Statement to override values on wires or registers. It is typically used with a simulator during design debugging to change signal values; however, it is not supported for synthesis, because you should never need to release the value on a wire or in a net in a synthesized design.

ACTION: Edit the design to remove the Release Statement.