ID:13474 Verilog HDL Defparam Statement error at <location>: parameter "<name>" cannot be assigned to its own value -- can't resolve self-referential loop

CAUSE: In a Defparam Statement at the specified location in a Verilog Design File (.v), you assigned the specified parameter to its own value. This assignment creates a self-referential loop that Quartus Prime Integrated Synthesis cannot resolve. This message can occur because you intended to change the value of a similarly named parameter in a lower hierarchy.

ACTION: Remove the Defparam Statement, or remove the self-referential assignment from the Defparam Statement. If you intended to change the value of a similarly named parameter in a lower hierarchy, make sure you correctly prefix the parameter name with the name of the lower hierarchy.