ID:13426 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: UDP must have exactly one output port

CAUSE: In a User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you specified a UDP with no output port or with more than one output port; however, a UDP must have exactly one output port.

ACTION: Add a single output port to the UDP.