ID:13535 Verilog HDL Expression error at <location>: indexed name does not fully index unpacked array "<number>"

CAUSE: In an expression at the specified location in a Verilog Design File (.v), you indexed the specified array. However, you did not provide enough indices to fully index the array. Verilog HDL does not allow references to all or part of an array.

ACTION: Provide as many indices as there are dimensions in the array, or change the Verilog Input Version to SystemVerilog-2005, which relaxes this restriction.