ID:13367 Verilog HDL Gate Instantiation error at <location>: gate requires at least one input and one output port

CAUSE: In a Gate Instantiation at the specified location in a Verilog Design File (.v), you instantiated a built-in logic gate; however, the gate is missing required ports. Basic logic gates require at least one input and one output connection to function correctly in the circuit.

ACTION: Add the missing input or output ports to the gate.