ID:13526 Verilog HDL Module Instantiation error at <location>: instance "<name>" specifies <number> actual port connections but module "<name>" only expects <number>

CAUSE: In a Verilog Design File (.v), you instantiated a module and connected to the module using an Ordered Part Connect List. However, the number of port connections you connected to the instance exceeds the number of ports declared by the Module Declaration.

ACTION: Check the declaration of the Module Instantiation for the number of ports declared.