ID:13396 Verilog HDL Declaration error at <location>: identifier "<name>" is already declared in the present scope

CAUSE: In a Verilog Declaration at the specified location in a Verilog Design File (.v), you used an identifier to declare an object. However, you already used the identifier to declare another object in the present scope. You may use an identifier to declare at most one object in a scope. If this error occurs for a port of a module, you may have declared that port as a wire or reg type before declaring it as a port of input, output or inout type. Ports must be declared as an input, output or inout type before they are declared as a wire or reg type.

ACTION: Remove the duplicate declaration from the design. If the duplicated declaration is a port, make sure the port is declared as an input, output or inout type before declaring the port as a wire or reg type.