ID:13326 Verilog HDL Always Construct error at <location>: Force Statement is not supported for processing with Quartus Prime Integrated Synthesis

CAUSE: In an Always Construct at the specified location in a Verilog Design File (.v), you used a Force Statement. Although Force Statements are supported in Verilog HDL, they are not supported for processing with Quartus Prime Integrated Synthesis. A Force Statement is used in conjunction with a Release Statement to override values on wires or registers. It is typically used with a simulator during design debugging to change signal values; however, it is not supported for synthesis, because you should never need to release the value on a wire or in a net in a synthesized design.

ACTION: Edit the design to remove the Force Statement.