ID:13343 Verilog HDL error at <location>: ports are defined with expressions -- must use standard Verilog HDL statements to instantiate modules
CAUSE: In a Verilog Design File (.v) at the specified location, you defined some ports by using Verilog HDL expressions. You must use standard Verilog HDL statements to instantiate modules.
ACTION: Use standard Verilog HDL statements, such as Module Definition and Module Instantiation statements, to instantiate modules.