ID:13462 Verilog HDL Compiler Directive error at <location>: nested 'ifdef or 'ifndef block exceeds nesting limit of <number>

CAUSE: In a Verilog Design File (.v) at the specified location, you used a `ifdef or `ifndef compiler directive to begin a nested block that exceeds the specified nesting limit for Quartus Prime Integrated Synthesis.

ACTION: Limit the nesting of 'ifdef or 'ifndef blocks so you do not exceed the nesting limit for Quartus Prime Integrated Synthesis.