ID:13442 Verilog HDL Declaration error at <location>: vector has more than 2**<number> bits

CAUSE: In a Verilog Design File (.v) at the specified location, you declared a vector with more than 2**20 bits. Quartus Prime Integrated Synthesis does not support vectors with more than 2**20 bits.

ACTION: Reduce the size of the vector, or declare the vector as an array.