ID:13358 Verilog HDL Compiler Directive error at <location>: missing Compiler Directive

CAUSE: In a Verilog Design File (.v) at the specified location, you used what appears to be a Compiler Directive (such as `define); however, the Compiler Directive keyword you used is not recognized by Quartus Prime Integrated Synthesis.

ACTION: Edit the design to use the correct Compiler Directive keyword.