ID:13495 Verilog HDL Module Instantiation error at <location>: cannot elaborate array of instances because the instances do not have a consistent width for port "<port name>"

CAUSE: In a Verilog Design File (.v) at the specified location, you instantiated an array of instances. However, the instances have different widths for the specified port. The special port connection rules defined by Verilog HDL require that all instances in the array have identical widths for all ports.

ACTION: Check your parameter overrides for the instances in the array. In particular, look for Defparam Statements that might alter the port widths in instantiated module. Remove or modify the Defparam Statements to achieve a consistent width for the specified port in all instances in the array.