ID:13267 The port was declared at <location>

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you declared the specified object at the specified location. This message provides additional information for prior message(s) in the Messages window or in the Analysis & Synthesis Messages section of the Report window.

ACTION: Use the information provided by this message to diagnose and resolve prior warnings or errors.