ID:13237 Can't create symbol/include/instantiation/component file for module "<name>" with list of ports that includes part select(s), bit select(s), concatenation(s), or explicit port(s)

CAUSE: You attempted to create a symbol/include/instantiation/component file for the specified module in a Verilog Design File (.vhd). However, the module was declared with a list of ports that includes one or more port expressions that are not simple identifiers. The Quartus Prime software cannot generate symbol/AHDL/VHDL/Verilog ports for more complicated port expressions.

ACTION: Use only simple identifiers as port expressions if you wish to generate a symbol/include/instantiation/component file for this module.