ID:13567 Verilog HDL Unsupported Feature error at <location>: support for multiple packed dimensions available only in SystemVerilog mode

CAUSE: In a data type declaration at the specified location in a Verilog Design File(.v), you declared an object with more than one packed dimension. (Packed dimensions precede the object identifier in the declaration.) In Verilog HDL, you may specify a single packed dimension. In SystemVerilog, however, you may specify an arbitrary number of packed dimensions.

ACTION: Change your Verilog HDL Input Version to SystemVerilog, or remove the extra packed dimensions from the object declaration. Alternatively, you can declare the extra packed dimensions as unpacked dimensions, which follow the object identifier in the declaration. Both Verilog HDL and SystemVerilog support an arbitrary number of unpacked dimensions. However, be aware that unpacked arrays behave differently than packed arrays.