ID:13250 Can't use synthesis directive or attribute "<name>" when running in <name> mode

CAUSE: In a Verilog Design File (.v) or a VHDL Design File (.vhd), you used the specified synthesis directive or attribute. However, you also specified an EDA formal verification tool that does not recognize the specified synthesis directive or attribute. As a result, the EDA formal verification tool may report a mismatch between the synthesized netlist and your HDL.

ACTION: Remove the specified synthesis directive or attribute from the design file, or refrain from specifying an EDA formal verification tool in your project settings.