ID:13263 Can't elaborate Greybox netlist for module or entity "<name>" at <location> - Integrated Synthesis requires the actual module or entity

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), the specified module or entity was declared with the synthesis_greybox attribute, indicating that the module or entity represents a greybox netlist, which should be used only by an external EDA synthesis tool. When compiling the design with Integrated Synthesis, you must use the actual module or entity.

ACTION: Remove the file containing the greybox netlist from your project, and include the file with the actual module or entity.