ID:288014 Port "<name>" in the port list of the Module Declaration for entity "<name>" not declared within the module

CAUSE: In the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, the specified port is declared in the port list of the Module Declaration for the specified entity. However, the port is not declared within the module.

ACTION: Declare the specified port within the module. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.