ID:288004 Module Instantiation error: port "<name>" is in the named port connection list of a Module Instantiation, but the port is not defined in the Module Declaration for instantiated module "<name>"

CAUSE: In the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, you listed the specified port in the named port connection list of a Module Instantiation, but you did not define the port in the Module Declaration of the instantiated module. A port in the named port connection list for an instantiated module must also be in the Module Declaration for the module. This error may also have occurred if you created or edited a VQM File manually.

ACTION: Remove the port from the Module Instantiation, or define the port in the Module Declaration. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.