ID:288011 Input port "<name>" cannot be assigned a value

CAUSE: In the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, you assigned a value to the specified input port by using the port on the left of a Continuous Assignment. You cannot assign a value to an input port; in a Continuous Assignment, you must use an input port only on the right of the assignment (that is, as a value). This error may also have occurred if you created or edited a VQM File manually.

ACTION: Replace the input port on the left of the Continuous Assignment with a legal net, constant bit-select or part-select of a vector net, or a concatenation of these items. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.