ID:146014 Logic level(s) do not match expected level(s)

CAUSE: You compared the expected versus actual outputs of simulation. The Simulator determined that the output of simulation did not match the expected outputs in the specified vector source file in some way, although the output of simulation levels did match the expected outputs of the common signals.

ACTION: Click the + icon to expand this message in the Messages window and display details about how the specified compared files do not match. You can Simulation Waveforms section of the Simulation Report and either correct the expected outputs in the vector source file or correct the design file.