ID:283001 Can't create Component Declaration or Verilog Instantiation File for entity "<name>" which has two or more dimensional ports

CAUSE: You attempted to create a VHDL Component Declaration File (.cmp) or a Verilog Instantiation File (_inst.v) for an entity which has two or more dimensional ports. Two or more dimensional ports entities are not supported in the current release of the Quartus Prime software.

ACTION: Remove the extra dimensional ports from the entity, or change the entity type to support the extra dimensional ports.