ID:276001 Cannot synthesize dual-port RAM logic "<name>"

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you specified logic that acts as RAM with at least two write ports, but Analysis & Synthesis can map the RAM write logic only to the same process block.

ACTION: If you intend to infer the RAM into the hardware, refer to Chapter 6, "Recommended HDL Coding Styles," in the Quartus Prime Handbook, vol. 1., for examples of coding styles that allow Analysis & Synthesis to infer RAM. If the RAM is not meant to be inferred into hardware, move the RAM write logic to the same always or process block.