ID:11575 ATX PLL node "<name>" uses an output frequency of <name> MHz that exceeds the maximum frequency of <name> MHz for GT parts in the targeted speed grade "<name>" for a <name> ATX PLL in a transceiver bank on the <name> side of the device.
CAUSE: The Auxiliary Transmit Phase-Locked Loop (ATX PLL) output frequency exceeds the maximum frequency of the placed location.
ACTION: Refer to the Stratix V Errata document to determine the correct speed grade and PLL location for the ATX PLL to support the desired output frequency.