ID:275076 Can't create HDL Design File because TRI primitive "<name>" missing signal(s)
CAUSE: You created a TRI primitive is missing one or more input, output enable, or output signals. The Quartus Prime software cannot convert a TRI primitive without properly connected input, output enable, or output signals into a valid group of VHDL or Verilog statements.
ACTION: Make sure the necessary input, output enable, and output signals are connected to the TRI primitive and create the HDL design file again.