ID:275075 Can't create HDL Design File because <name> primitive "<name>" is missing necessary signal(s)

CAUSE: You created a Graphic Design File (.gdf), but the specified flipflop primitive is missing one or more necessary input, output, or clock signals. The Quartus Prime software cannot convert a flipflop primitive without properly connected input, output, or clock signals into a valid group of VHDL or Verilog statements.

ACTION: Make sure the necessary data input, output, and clock signals are connected to the flipflop primitive and create the HDL design file again.