ID:275068 Design name "<type_name>" is illegal for VHDL

CAUSE: You created a VHDL Design File (.vhd) from the current design file. However, the current design name contains an illegal character for Verilog HDL, "/", "_", or "-", or contains a VHDL keyword. This can cause the VHDL Design File to not compile once it is generated.

ACTION: Rename the design to exclude illegal name characters or VHDL keywords and create the HDL design file again.