ID:176591 Input clock of Fast PLL "<name>" cannot use global or regional clock because the Fast PLL drives a SERDES receiver that does not use dynamic phase alignment

CAUSE: You set the Global Signal logic option with a value of global clock or regional clock to an input clock of the specified Fast PLL. However, the Fitter cannot route the signal using both of the clock assignments because the Fast PLL drives a SERDES receiver that does not use dynamic phase alignment (DPA). The timing requirements for the Fast PLL will not be met if a global or a regional clock is used.

ACTION: Delete the global signal assignments from the input clock to the specified Fast PLL.