ID:176167 Fast PLL <name> has input clock <name> with I/O standard <name>. This PLL drives differential I/O pins having I/O standard <name>. Clock and data I/O standards should be the same. This might happen if input clock drives two or more PLLs with different I/O standard on their differential I/O pins.

CAUSE: The input clock pin drives more than one fast PLL. You assigned different differential I/O standards to the input clock and the differential I/O pins of at least one of the fast PLLs.

ACTION: Modify design so the input clock and all differential I/O pins of the fast PLLs driven by this input clock have the same differential I/O standard.