ID:170035 Logic Lock region <name> is too small to contain its members

CAUSE: You created a Logic Lock region and assigned the specified cells to the region. However, the Fitter is unable to satisfy this constraint. On or more of the reasons are:

• The assignments require more entities in this region than the device can contain.
• If the entities are LABs, the Fitter was unable to divide the related logic cells into a small enough number of LABs so that they will all fit in the specified region.
• There are carry and cascade chains, and limitations on the number of clock enables, clocks, asynchronous clears and so on per LAB. The Fitter is unable to divide all the logic cells assigned to a region into a small enough number of legal LABs to fit in that region.
• If the entities are RAM cells, the Fitter is unable to divide them into a small enough number of memory block locations so that they will all fit in the specified region. Different address and control lines or different modes may prevent two RAM cells from sharing the same memory block.
• There are Logic Lock regions in the design. The design elements assigned to one or more of these regions require more resource blocks than the regions contain.
• Resource blocks of the specified type that are in the region are also covered by a Logic Lock region with the Reserved property set to On or Limited. The Fitter cannot use these resource blocks to fit design elements that are not members of the reserved Logic Lock region.

ACTION: Depending on the cause, one or more of the following actions may resolve the problem:

• Adjust the size and/or origin of the region to make sure that it covers enough resource blocks for its members. In addition, make sure that the required resource blocks are not also covered by another Logic Lock region with the Reserved property set to On or Limited.
• Consider setting the region size and origin to Auto and Floating, respectively. This allows the Fitter to automatically determine a feasible region placement.
• Reduce the region's resource requirement, by eliminating some or all of its members requiring the specified resource type. You may also fine-tune existing region memberships by specifying a list of Excluded Element Types for each Logic Lock membership assignment (for example, to exclude all design elements of type DSP from being assigned to the region).
• Reduce the amount of logic in the design.
• Select a larger device.