ID:181030 DDR circuitry in DQ I/O pin "<number>" is driven by too many DQS Delay Chain primitives

CAUSE: The Fitter determined that DDR circuitry associated with the specified DQ I/O is associated with too many DQSBUS signals. DDR circuitry in an I/O pin can be clocked by only one DQSBUS and possibly one nDQSBUS if the I/O pin is configured to use QDR mode. DQSBUS signals are driven by DQS_DELAY_CHAIN primitives.

ACTION: Modify your design to ensure that the circuitry in the specified DQ pin is not driven by more than one DQSBUS.