ID:15898 PLL "<name>" has port <name> connected but parameters <name> and/or <name> are either unspecified or set to 0

CAUSE: The specified clock output port of the specified PLL is connected, but the clock multiply_by or divide_by parameters are not correctly specified. All output clock ports that are used must have valid multiply and divide settings.

ACTION: Specify the multiply_by and divide_by parameters or disconnect the specified clock output port.